Nested Quantization Index Modulation for Reversible Watermarking and Its Application to Healthcare Information Management Systems

Digital watermarking has attracted lots of researches to healthcare information management systems for access control, patients' data protection, and information retrieval. The well-known quantization index modulation-(QIM-) based watermarking has its limitations as the host image will be destroyed; however, the recovery of medical images is essential to avoid misdiagnosis. In this paper, we propose the nested QIM-based watermarking, which is preferable to the QIM-based watermarking for the medical image applications. As the host image can be exactly reconstructed by the nested QIM-based watermarking. The capacity of the embedded watermark can be increased by taking advantage of the proposed nest structure. The algorithm and mathematical model of the nested QIM-based watermarking including forward and inverse model is presented. Due to algorithms and architectures of forward and inverse nested QIM, the concurrent programs and special processors for the nested QIM-based watermarking are easily implemented

Haar-Wavelet-Based Just Noticeable Distortion Model for Transparent Watermark

Watermark transparency is required mainly for copyright protection. Based on the characteristics of human visual system, the just noticeable distortion (JND) can be used to verify the transparency requirement. More specifically, any watermarks whose intensities are less than the JND values of an image can be added without degrading the visual quality. It takes extensive experimentations for an appropriate JND model. Motivated by the texture masking effect and the spatial masking effect, which are key factors of JND, Chou and Li (1995) proposed the well-known full-band JND model for the transparent watermark applications. In this paper, we propose a novel JND model based on discrete wavelet transform. Experimental results show that the performance of the proposed JND model is comparable to that of the full-band JND model. However, it has the advantage of saving a lot of computation time; the speed is about 6 times faster than that of the full-band JND model

Application of Three-Repetition Tests Scheme to Improve Integrated Circuits Test Quality to Near-Zero Defect

In this research, the normal distribution is assumed to be the product characteristic, and the DITM (Digital Integrated Circuit Test Model) model is used to evaluate the integrated circuits (IC) test yield and test quality. Testing technology lags far behind manufacturing technology due to the different rates of development of the two technologies. As a result, quality control will pose significant challenges in pursuing high-quality near-zero defect products (automotive and biomedical electronics and avionics, etc.). In order to ensure product quality, we propose an effective repeated testing method (three-repetition tests scheme, TRTS), which utilizes the move test guardband (TGB) to improve the test yield and test quality. Based on the data in the International Roadmap for Devices and Systems table in 2021, the DITM model is used to estimate the future trend of semiconductor chip test yield, and the retest method (TRTS) is applied improve the test results. The method of repeated testing can increase the test yield and increase the shipment of semiconductor products. By estimating the test cost and profit, the method of repeated testing can obtain chips with near-zero defects with more corporate profits through increased product shipments

Unbalanced-Tests to the Improvement of Yield and Quality

An integrated-circuit testing model (DITM) is used to describe various factors that affect test yield during a test process. We used a probability distribution model to evaluate test yield and quality and introduced a threshold test and a guardband test. As a result of the development speed of the semiconductor manufacturing industry in the future being unpredictable, we use electrical properties of existing products and the current manufacturing technology to estimate future product-distribution trends. In the development of very-large-scale integration (VLSI) testing, the progress of testing technology is very slow. To improve product testing yield and quality, we change the test method and propose an unbalanced-test method, leading to improvements in test results. The calculation using our proposed model and data estimated by the product published by the IEEE International Roadmap for Devices and Systems (IRDS, 2017) proves that the proposed unbalanced-test method can greatly improve test yield and quality and achieve the goal of high-quality, near-zero-defect products

Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits

In this paper, an approach to generating the sinusoidal stimulus of the right frequency of a linear analog circuit for testing circuit parameter faults under the constraints of the specifications of the circuit under test (CUT) is presented. This approach considers tolerance bounds due to fabrication process fluctuations of tested parameters using a statistical model and maps them to an accepted region of the observed signature of the CUT. The generated test stimulus is derived based on a proposed testing confidence level. Test generation procedures for both the monotonic and non-monotonic relationships between the signature and the parameter are proposed and demonstrated. The procedures are applied to a continuous time state-variable filter example circuit to show the effectiveness of the methodology

Using Enhanced Test Systems Based on Digital IC Test Model for the Improvement of Test Yield

In this work, we use statistical concepts to evaluate the joint probability distribution of manufacturing and test parameters and estimate the future trend of wafer test yield. Owing to the difference between the development speeds of testing technology and manufacturing technology, the testing capability of wafers is far behind the manufacturing capability of the semiconductor. Therefore, with the advancement in technology, the test yield loss caused by the tester inaccuracy has become an important problem. In this article, we propose an enhanced integrated circuit (IC) test scheme (ITS) that uses multiplex testing to improve test quality and test pass rate by retesting, and we rely on the cost evaluation mechanism to obtain the best test and the best profit. Furthermore, the International Roadmap for Devices and Systems (IRDS) 2017 data are used to estimate future test yield trends, and the results prove that the enhanced test scheme (ETS) can effectively estimate the best retest time to obtain the best test yield and the best profit

Using Enhanced Test Systems Based on Digital IC Test Model for the Improvement of Test Yield

In this work, we use statistical concepts to evaluate the joint probability distribution of manufacturing and test parameters and estimate the future trend of wafer test yield. Owing to the difference between the development speeds of testing technology and manufacturing technology, the testing capability of wafers is far behind the manufacturing capability of the semiconductor. Therefore, with the advancement in technology, the test yield loss caused by the tester inaccuracy has become an important problem. In this article, we propose an enhanced integrated circuit (IC) test scheme (ITS) that uses multiplex testing to improve test quality and test pass rate by retesting, and we rely on the cost evaluation mechanism to obtain the best test and the best profit. Furthermore, the International Roadmap for Devices and Systems (IRDS) 2017 data are used to estimate future test yield trends, and the results prove that the enhanced test scheme (ETS) can effectively estimate the best retest time to obtain the best test yield and the best profit

Multilevel full-chip routing with testability and yield enhancement

We propose in this paper a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. (1) The oscillation ring (OR) test and its diagnosis scheme for interconnect based on the popular IEEE P1500 are integrated into the multilevel routing framework to achieve testability enhancement. We augment the traditional multilevel framework of coarsening followed by uncoarsening by introducing a preprocessing stage that analyzes the oscillation ring structure for better resource estimation before the coarsening stage, and a final stage after uncoarsening that improves testability to achieve 100 % interconnect fault coverage and maximal diagnosability. (2) We present a heuristic to balance routing congestion to optimize the multiple-fault probability, chemical mechanic polishing (CMP) and optical proximity correction (OPC) induced manufacturability, and crosstalk effects, for yield improvement. Experimental results on the MCNC benchmark circuits show that the proposed OR method achieves 100 % fault coverage and the maximal diagnosis resolution for interconnects, and the multilevel routing algorithm effectively balances the routing density to achieve 100 % routing completion. Compared with [24], the experimental results show that our router improves the maximal congestion by 1.24X--6.11X in runtime speedup by 1.08X--7.66X, and improves the average congestion by 1.00X--4.52X with the improved congestion deviation by 1.37X--5.55X. 1